Senior Digital Hardware Design Engineer

Job Description

Do you enjoy challenging digital FPGA/ASIC design problems? HII Mission Technologies is seeking out-of-the-box thinkers who have a track record of successfully deploying designs and IP-targeting FPGAs or ASICs. Candidates should have a deep understanding of how their high-level RTL designs are realized at the gate-level of the device.
Candidates for this position will help lead teams of digital designers to utilize industry-standard FPGA design tools (e.g., Vivado, Quartus, ISE, Synplify, etc.) and proprietary software tools to not only implement new designs and IP, but reverse engineer the features and functions of those designs. Common functions of interest include embedded microprocessors, DSPs, filters, transceivers, data links, systems-on-chip, network switches, and decoders. Candidates will be expected to utilize experience in the cybersecurity, electronic warfare, encryption, radar, and/or satellite communications domains to provide perspective on digital design approaches.
 

Positions are available with our teams in Roanoke, VA or Huntsville, AL.

Essential Job Responsibilities

Candidates will develop IP cores and designs that help uncover common implementation features at the gate level and stress test proprietary hardware reverse-engineering software. They will also utilize past design and verification experience to develop new algorithms and processes for hardware reverse-engineering. Candidates will be expected to produce clear documentation on the methodology and assumptions made in uncovering the features, functions, and limitations of FPGA designs and their IP cores. Effective collaboration with teammates to produce cohesive results and create improved processes is required.

Candidates must be U.S. citizens and be willing and able to obtain a DoD security clearance (if not already cleared).

Minimum Qualifications

9 years relevant experience with a Bachelor's in a related field; 7 years relevant experience with a Master's in a related field; 4 years relevant experience with a PhD or Juris Doctorate in a related field; or High School Diploma or equivalent and 13 years relevant experience.

•    US Citizenship
•    Willingness to obtain a Top-Secret security clearance
•    Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
•    Experience with modern digital design and modeling languages: Verilog, SystemVerilog, VHDL, Matlab, etc.
•    Proven ability to synthesize, implement, and close timing on FPGA or ASIC designs and understand form/fit/function trade-offs
•    Experience with modern, commercial-grade, FPGA/ASIC implementation tools (e.g., ISE, Quartus, Synplify, Vivado, Design Compiler, Innovus, etc.)
•    Writing scripts for batched verification tasks: Python, Bash, Tcl, make files.
•    Revision control systems for maintaining, sharing, and deploying IP: Perforce, git, SVN, etc.
•    Familiarity with debugging and isolating issues with designs at the gate level (i.e, post layout and routing)
 

Preferred Requirements

•    Familiarity with EDA algorithms for synthesizing, mapping, placing/layout, routing, and timing closure for FPGAs or ASICs
•    Software reverse-engineering (e.g., IDA Pro, Ghidra) 
•    Digital hardware reverse-engineering
•    Directed testing or ABV of your design IP in a simulator
•    Active Secret or Top Secret security clearance
•    Familiarity with FPGA/ASIC security features and concepts
•    Experience with logical equivalence checkers (e.g., OneSpin 360-EC, ESP, Conformal EC)